From 1222a73205bd3a0faba988411b4aec6ea8de1059 Mon Sep 17 00:00:00 2001 From: Rizwan Qureshi Date: Tue, 23 Aug 2016 14:31:23 +0530 Subject: skylake: Add initial FSP2.0 support Add Initial pieces of code to support fsp2.0 in skylake keeping the fsp1.1 flow intact. The soc/romstage.h and soc/ramstage.h have a reference to fsp driver includes, so split these header files for each version of FSP driver. Add the below files, car_stage.S: Add romstage entry point (car_stage_entry). This calls into romstage_fsp20.c and aslo handles the car teardown. romstage_fsp20.c: Call fsp_memory_init() and also has the callback for filling memory init parameters. Also add monotonic_timer.c to verstage. With this patchset and relevant change in kunimitsu mainboard, we are able to boot to romstage. TEST= Build and Boot Kunimitsu with PLATFORM_USES_FSP1_1 Build and Boot Kunimitsu to romstage with PLATFORM_USES_FSP2_0 Change-Id: I4309c8d4369c84d2bd1b13e8ab7bfeaaec645520 Signed-off-by: Rizwan Qureshi Reviewed-on: https://review.coreboot.org/16267 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/Makefile.inc | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/skylake/Makefile.inc') diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 716c3d503f..aa3da61f22 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -40,12 +40,14 @@ romstage-y += pch.c romstage-y += pcr.c romstage-y += pei_data.c romstage-y += pmutil.c +romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c romstage-y += smbus_common.c romstage-y += tsc_freq.c romstage-$(CONFIG_UART_DEBUG) += uart_debug.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c -ramstage-y += chip.c +ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += chip.c +ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += chip_fsp20.c ramstage-y += cpu.c ramstage-y += cpu_info.c ramstage-y += dsp.c @@ -59,12 +61,14 @@ ramstage-y += lpc.c ramstage-y += me_status.c ramstage-y += memmap.c ramstage-y += monotonic_timer.c +ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += opregion.c ramstage-y += pch.c ramstage-y += pcie.c ramstage-y += pcr.c ramstage-y += pei_data.c ramstage-y += pmc.c ramstage-y += pmutil.c +ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c ramstage-y += ramstage.c ramstage-y += sd.c ramstage-y += smbus.c @@ -93,7 +97,14 @@ smm-$(CONFIG_UART_DEBUG) += uart_debug.c CPPFLAGS_common += -I$(src)/soc/intel/skylake CPPFLAGS_common += -I$(src)/soc/intel/skylake/include + +ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y) +CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp11 CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/skylake +else +CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp20 +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/skykabylake +endif # Currently used for microcode path. CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARD_DIR) -- cgit v1.2.3