From ffdf901c765db8bb01006fa81839fb5703eea4e1 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Fri, 24 Jul 2015 13:00:36 -0500 Subject: skylake: provide native gpio functionality It's important to be able to configure the gpio pads at various stages instead of a single place using FSP. Without this support there is a lot of duplicated open-coded pad configuration taking place both within the SoC code and mainboards. Current limitation is that all GPIOs are in ACPI mode. i.e. The HostSW ownership register sets the pad configuration to only update GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. The GPI_STS update is masked within the GPIO community registers. BUG=chrome-os-partner:42982 BRANCH=None TEST=Built and booted glados. Original-Change-Id: Id8a00e99c7a4c3912de2feaff9cea12b402f2c68 Original-Signed-off-by: Aaron Durbin Original-Reviewed-on: https://chromium-review.googlesource.com/289789 Original-Reviewed-by: Duncan Laurie Change-Id: I4c86b47ac5ab004f2bfd7cb07dd23c458f7dbb7c Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/11174 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/skylake/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/skylake/Kconfig') diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index e2c43f042e..6c64cd9925 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -20,6 +20,7 @@ config CPU_SPECIFIC_OPTIONS select COLLECT_TIMESTAMPS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_MICROCODE_IN_CBFS + select GENERIC_GPIO_LIB select HAS_PRECBMEM_TIMESTAMP_REGION select HAVE_HARD_RESET select HAVE_MONOTONIC_TIMER -- cgit v1.2.3