From fbdc71941454cd4f6dbaebb3e38d27d11ab256ea Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 19 Jan 2016 19:19:15 +0530 Subject: intel/skylake: Implement native Cache-as-RAM (CAR) Now coreboot should do BIOS CAR setup along with NEM mode setup. This patch also provides a mechanism to use 16MB code caching benefit although LLC still limited to 1M/1.5M based on SOC LLC limit. Here with unlimited cache line gets replaced. Now we could use unlimited cache size along with well defined data size [pg: updated to current upstream #defines] BUG=chrome-os-partner:48412 BRANCH=glados TEST=Builds and Boots on FAB4 SKU2/3. Signed-off-by: Subrata Banik Signed-off-by: pchandri Signed-off-by: Dhaval Sharma Change-Id: I96a9cf3a6e41cae9619c683dca28ad31dcaa2536 Signed-off-by: Patrick Georgi Original-Commit-Id: 2ec51f15c874ad2f1f4fad52fa8deced7b27a24b Original-Change-Id: Id62c15799d98bc27b5e558adfa7c7b3468aa153a Original-Reviewed-on: https://chromium-review.googlesource.com/320855 Original-Commit-Ready: Subrata Banik Original-Tested-by: Subrata Banik Original-Reviewed-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/13138 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/intel/skylake/Kconfig | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/soc/intel/skylake/Kconfig') diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 58b828fd17..35b2a18ee6 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -176,4 +176,14 @@ config NHLT_SSM4567 help Include DSP firmware settings for ssm4567 smart amplifier. +config DCACHE_RAM_SIZE_TOTAL + hex + default 0x40000 + +config SKIP_FSP_CAR + bool "Skip cache as RAM setup in FSP" + default y + help + Skip Cache as RAM setup in FSP. + endif -- cgit v1.2.3