From 551e4be7301eca04104c8f0d4379b906dfb07c1b Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 10 Apr 2018 09:24:54 -0600 Subject: soc/intel/common: prepare for lpss clock split Apparently Intel had decided to use different clock speeds for some of its IP blocks in some of its designs. The i2c designware driver has already been moved into common code allowing for its own Kconfig value. That currently leaves SPI (UART isn't using the clock currently). Therefore, remove SOC_INTEL_COMMON_LPSS_CLOCK_MHZ and add SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ to allow for the different clock speeds present in the system for the various IP blocks. BUG=b:75306520 Change-Id: I6cb8c2de0ff446b6006bc37645fca64f2b70bf17 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/25608 Reviewed-by: Furquan Shaikh Reviewed-by: Hannah Williams Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/skylake/Kconfig') diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index cf947a7670..326b84722a 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -338,13 +338,13 @@ config NO_FADT_8042 help Choose this option if you want to disable 8042 Keyboard -config SOC_INTEL_COMMON_LPSS_CLOCK_MHZ +config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ int default 120 config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int - default SOC_INTEL_COMMON_LPSS_CLOCK_MHZ + default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ config SOC_INTEL_COMMON_BLOCK_GSPI_MAX int -- cgit v1.2.3