From 4bab6e79b078c76d0a42883c4b4c9c68615d5a1e Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Tue, 3 May 2016 15:53:33 -0700 Subject: intel/sch: Merge northbridge and southbridge in src/soc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I6ea9b9d2353c0d767c837e6d629b45f23b306f6e Signed-off-by: Stefan Reinauer Reviewed-on: https://review.coreboot.org/14599 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Vladimir Serbinenko --- src/soc/intel/sch/usb_ehci.c | 91 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 src/soc/intel/sch/usb_ehci.c (limited to 'src/soc/intel/sch/usb_ehci.c') diff --git a/src/soc/intel/sch/usb_ehci.c b/src/soc/intel/sch/usb_ehci.c new file mode 100644 index 0000000000..8191d0aba7 --- /dev/null +++ b/src/soc/intel/sch/usb_ehci.c @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2010 coresystems GmbH + * Copyright (C) 2009-2010 iWave Systems + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +static void usb_ehci_init(struct device *dev) +{ + u32 reg32; + + printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + /* Disable clock gating */ +#if 0 + reg32 = pci_read_config32(dev, 0xc0); + reg32 |= (1 << 2); + pci_write_config32(dev, 0xc0, reg32); +#endif + // pci_write_config32(dev, 0x3c, 0x17); + reg32 = pci_read_config32(dev, 0xFC); + reg32 |= (1 << 28); + pci_write_config32(dev, 0xFC, reg32); + + reg32 = pci_read_config32(dev, 0x4); + printk(BIOS_DEBUG, "PCI_COMMAND %x.\n", reg32); + reg32 = pci_read_config32(dev, 0x20); + printk(BIOS_DEBUG, "PCI_BASE %x.\n", reg32); + reg32 = pci_read_config32(dev, 0xC0); + printk(BIOS_DEBUG, "PCI_FD %x.\n", reg32); + printk(BIOS_DEBUG, "done.\n"); +} + +static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, + unsigned device) +{ + u8 access_cntl; + + access_cntl = pci_read_config8(dev, 0x80); + + /* Enable writes to protected registers. */ + pci_write_config8(dev, 0x80, access_cntl | 1); + + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } + + /* Restore protection. */ + pci_write_config8(dev, 0x80, access_cntl); +} + +static struct pci_operations lops_pci = { + .set_subsystem = &usb_ehci_set_subsystem, +}; + +static struct device_operations usb_ehci_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = usb_ehci_init, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver sch_usb_ehci __pci_driver = { + .ops = &usb_ehci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x8117, +}; -- cgit v1.2.3