From d5f645c6cde230004ee5af6c62d451d1329928e9 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sat, 28 Sep 2019 00:20:27 +0300 Subject: soc/intel: Replace config_of_path() with config_of_soc() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The previously provided device path made no difference, all integrated PCI devices point back to the same chip_info structure. Change reduces the exposure of various SA_DEVFN_xx and PCH_DEVFN_xx from (ugly) soc/pci_devs.h. Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35656 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/quark/romstage/fsp2_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/quark') diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index a64fed4868..cd654d74de 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -93,7 +93,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) "Microcode file (rmu.bin) not found."); /* Locate the configuration data from devicetree.cb */ - config = config_of_path(LPC_DEV_FUNC); + config = config_of_soc(); /* Update the architectural UPD values. */ aupd = &fspm_upd->FspmArchUpd; -- cgit v1.2.3