From e613d704d12592dfc371d81957a3d83b0742fa7d Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Tue, 12 Feb 2019 14:16:21 +0200 Subject: console: Split loglevel for fast and slow MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For fast CBMEM console use minimum BIOS_DEBUG level. For other consoles, Kconfig and/or nvram settings apply. Change-Id: Iff56a0a3182f258200cac80e013957d598cc2130 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/31370 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/intel/quark/romstage/fsp2_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/quark/romstage/fsp2_0.c') diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 23051bde6d..c237da5270 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -173,7 +173,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) upd->RankMask = config->RankMask; upd->RmuBaseAddress = (uintptr_t)rmu_data; upd->RmuLength = rmu_data_len; - upd->SerialPortWriteChar = console_log_level(BIOS_SPEW) + upd->SerialPortWriteChar = !!console_log_level(BIOS_SPEW) ? (uintptr_t)fsp_write_line : 0; upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? config->SmmTsegSize : 0; -- cgit v1.2.3