From a7ba56e3ce56c8569e2ac5ddb2d2b6c71458d9cb Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Sun, 7 Feb 2016 10:42:14 -0800 Subject: soc/intel/quark: Add TempRamInit support Successfully invoke TempRamInit from the FSP binary: * Don't relocate the FSP binary image * Copy the FSP binary into ESRAM * Specify Kconfig values to easily debug ESRAM and TempRamInit code * Specify the FSP binary file location * Specify the FSP binary image ID * Specify where in the flash image the FSP image must reside * Specify the FSP data file location * Specify where to place the FSP data file in the flash image * Specify where in the ESRAM the FSP image must reside Test 1 on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Add "select ENABLE_DEBUG_LED_FINDFSP" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if the SD LED is on indicating that the FSP.bin file was properly located, The test fails if the SD LED is flashing. Test 2 on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Remove "select ENABLE_DEBUG_LED_FINDFSP" * Add "select ENABLE_DEBUG_LED_TEMPRAMINIT" * Testing is successful if the SD LED is on indicating that the FSP.bin file was properly located, The test fails if the SD LED is flashing. Change-Id: I1e2e413a8573f750c611b0f9df101b2c869a789e Signed-off-by: Lee Leahy Reviewed-on: https://review.coreboot.org/13443 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/quark/Kconfig | 118 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 118 insertions(+) (limited to 'src/soc/intel/quark/Kconfig') diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 1bfab49c95..802f972058 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -28,6 +28,42 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select USE_MARCH_586 +##### +# Debug support +# The following options provide debug support for the Quark coreboot +# code. The SD LED is used as a binary marker to determine if a +# specific point in the execution flow has been reached. +##### + +config ENABLE_DEBUG_LED + bool + default n + help + Enable the use of the SD LED for early debugging before serial output + is available. Setting this LED indicates that control has reached the + desired check point. + +config ENABLE_DEBUG_LED_ESRAM + bool "SD LED indicates ESRAM initialized" + default n + select ENABLE_DEBUG_LED + help + Indicate that ESRAM has been successfully initialized. + +config ENABLE_DEBUG_LED_FINDFSP + bool "SD LED indicates fsp.bin file was found" + default n + select ENABLE_DEBUG_LED + help + Indicate that fsp.bin was found. + +config ENABLE_DEBUG_LED_TEMPRAMINIT + bool "SD LED indicates TempRamInit was successful" + default n + select ENABLE_DEBUG_LED + help + Indicate that TempRamInit was successful. + ##### # Flash layout # Specify the size of the coreboot file system in the read-only @@ -44,6 +80,88 @@ config CBFS_SIZE - The chipset microcode (RMU) binary file located at 0xFFF00000 - Intel Trusted Execution Engine firmware +##### +# FSP binary +# The following options control the FSP binary file placement in +# the flash image and ESRAM. This file is required by the Quark +# SoC code to boot coreboot and its payload. +##### + +config ADD_FSP_RAW_BIN + bool "Add the Intel FSP binary to the flash image without relocation" + default n + depends on PLATFORM_USES_FSP1_1 + help + Select this option to add an Intel FSP binary to + the resulting coreboot image. + + Note: Without this binary, coreboot builds relying on the FSP + will not boot + +config FSP_FILE + string "Intel FSP binary path and filename" + default "3rdparty/blobs/soc/intel/quark/fsp.bin" + depends on PLATFORM_USES_FSP1_1 + depends on ADD_FSP_RAW_BIN + help + The path and filename of the Intel FSP binary for this platform. + +config FSP_IMAGE_ID_STRING + string "8 byte platform string identifying the FSP platform" + default "QUK-FSP0" + depends on PLATFORM_USES_FSP1_1 + help + 8 ASCII character byte signature string that will help match the FSP + binary to a supported hardware configuration. + +config FSP_LOC + hex + default 0xfff80000 + depends on PLATFORM_USES_FSP1_1 + help + The location in CBFS that the FSP is located. This must match the + value that is set in the FSP binary. If the FSP needs to be moved, + rebase the FSP with Intel's BCT (tool). + +config FSP_ESRAM_LOC + hex + default 0x80000000 + depends on PLATFORM_USES_FSP1_1 + help + The location in ESRAM where a copy of the FSP binary is placed. + +##### +# FSP PDAT binary +# The following options control the FSP platform data binary +# file placement in the flash image. +##### + +config ADD_FSP_PDAT_FILE + bool "Should the PDAT binary be added to the flash image?" + default n + depends on PLATFORM_USES_FSP1_1 + help + The PDAT file is required for the FSP 1.1 binary + +config FSP_PDAT_FILE + string + default "3rdparty/blobs/soc/intel/quark/pdat.bin" + depends on PLATFORM_USES_FSP1_1 + depends on ADD_FSP_PDAT_FILE + help + The path and filename of the Intel Galileo platform-data-patch (PDAT) + binary. This binary file is generated by the platform-data-patch.py + script released with the Quark BSP and contains the Ethernet address. + +config FSP_PDAT_LOC + hex + default 0xfff10000 + depends on PLATFORM_USES_FSP1_1 + depends on ADD_FSP_PDAT_FILE + help + The location in CBFS that the PDAT is located. It must match the + PCD PcdPlatformDataBaseAddress of Quark SoC FSP. + ##### # RMU binary # The following options control the Quark chipset microcode file -- cgit v1.2.3