From 7e0c771c50abbab6ff28483f75c5e3ae19de3301 Mon Sep 17 00:00:00 2001 From: Jamie Ryu Date: Tue, 5 Nov 2024 12:02:26 -0800 Subject: soc/intel/pantherlake: Update power limits config This updates power_limits_config for Panther Lake U and H. Source: Intel PTL PDG 813278 Intel PTL FSP Power limit profiles table BUG=b:357011633 TEST=Build fatcat and boot with Panther Lake SoC and RVP. Change-Id: I1b9276af7f1e30b1cda3d8c016524fd6397fa4b2 Signed-off-by: Jamie Ryu Reviewed-on: https://review.coreboot.org/c/coreboot/+/85006 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Wonkyu Kim --- src/soc/intel/pantherlake/chip.h | 6 +++--- src/soc/intel/pantherlake/chipset.cb | 12 ++++++------ 2 files changed, 9 insertions(+), 9 deletions(-) (limited to 'src/soc/intel/pantherlake') diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index 59aad4f7ce..b59ce5e8e6 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -65,9 +65,9 @@ static const struct { } cpuid_to_ptl[] = { { PCI_DID_INTEL_PTL_U_ID_1, PTL_U_1_CORE, TDP_15W }, { PCI_DID_INTEL_PTL_H_ID_1, PTL_H_1_CORE, TDP_25W }, - { PCI_DID_INTEL_PTL_H_ID_2, PTL_H_3_CORE, TDP_45W }, - { PCI_DID_INTEL_PTL_H_ID_3, PTL_H_1_CORE, TDP_25W }, - { PCI_DID_INTEL_PTL_H_ID_4, PTL_H_1_CORE, TDP_25W }, + { PCI_DID_INTEL_PTL_H_ID_2, PTL_H_1_CORE, TDP_25W }, + { PCI_DID_INTEL_PTL_H_ID_3, PTL_H_2_CORE, TDP_25W }, + { PCI_DID_INTEL_PTL_H_ID_4, PTL_H_2_CORE, TDP_25W }, }; /* Types of display ports */ diff --git a/src/soc/intel/pantherlake/chipset.cb b/src/soc/intel/pantherlake/chipset.cb index 4f6c8e0436..f4c1b265d9 100644 --- a/src/soc/intel/pantherlake/chipset.cb +++ b/src/soc/intel/pantherlake/chipset.cb @@ -4,20 +4,20 @@ chip soc/intel/pantherlake register "power_limits_config[PTL_U_1_CORE]" = "{ .tdp_pl1_override = 15, - .tdp_pl2_override = 54, - .tdp_pl4 = 142, + .tdp_pl2_override = 55, + .tdp_pl4 = 152, }" register "power_limits_config[PTL_H_1_CORE]" = "{ .tdp_pl1_override = 25, - .tdp_pl2_override = 64, - .tdp_pl4 = 154, + .tdp_pl2_override = 95, + .tdp_pl4 = 239, }" register "power_limits_config[PTL_H_2_CORE]" = "{ .tdp_pl1_override = 25, - .tdp_pl2_override = 80, - .tdp_pl4 = 240, + .tdp_pl2_override = 64, + .tdp_pl4 = 154, }" # NOTE: if any variant wants to override this value, use the same format -- cgit v1.2.3