From 1005e49580467437cdbe2db8f0c3b6c9b81da357 Mon Sep 17 00:00:00 2001 From: Jeremy Compostella Date: Fri, 20 Sep 2024 12:13:11 -0700 Subject: soc/intel/ptl: Remove tcss_d3_hot_disable en config structure field This commit drops tcss_d3_hot_disable chip config as FSP is not exposing the same purpose UPD anymore starting with Panther Lake SoC. BUG=b:348678529 TEST=Build for fatcat Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d58 Signed-off-by: Jeremy Compostella Reviewed-on: https://review.coreboot.org/c/coreboot/+/84441 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Pranava Y N Reviewed-by: Ronak Kanabar --- src/soc/intel/pantherlake/chip.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/soc/intel/pantherlake') diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index 9d8bec6ee4..d9028653a6 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -172,8 +172,6 @@ struct soc_intel_pantherlake_config { /* Enable S0iX support */ bool s0ix_enable; - /* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */ - bool tcss_d3_hot_disable; /* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */ bool tcss_d3_cold_disable; /* Enable DPTF support */ -- cgit v1.2.3