From 95cf9c0052234cf19599c03ea214eff4a6ed3b65 Mon Sep 17 00:00:00 2001 From: Saurabh Mishra Date: Thu, 12 Sep 2024 10:52:56 +0530 Subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit List of changes: 1. Add required SoC programming till ramstage. 2. Include only required headers into include/soc. 3. Skeleton code used to call FSP-S API. BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: I61930726ad0c765bfa1d72c5df893262be884834 Signed-off-by: Saurabh Mishra Reviewed-on: https://review.coreboot.org/c/coreboot/+/84332 Reviewed-by: Jérémy Compostella Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/soc/intel/pantherlake/gspi.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 src/soc/intel/pantherlake/gspi.c (limited to 'src/soc/intel/pantherlake/gspi.c') diff --git a/src/soc/intel/pantherlake/gspi.c b/src/soc/intel/pantherlake/gspi.c new file mode 100644 index 0000000000..387d3e3949 --- /dev/null +++ b/src/soc/intel/pantherlake/gspi.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +int gspi_soc_bus_to_devfn(unsigned int gspi_bus) +{ + switch (gspi_bus) { + case 0: + return PCI_DEVFN_GSPI0; + case 1: + return PCI_DEVFN_GSPI1; + case 2: + return PCI_DEVFN_GSPI2; + } + return -1; +} -- cgit v1.2.3