From de1a74454ffaaca11c6735814ad1b97cc6e522cd Mon Sep 17 00:00:00 2001 From: Saurabh Mishra Date: Wed, 24 Jul 2024 20:26:27 +0530 Subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit List of changes: 1. Add required SoC programming till romstage 2. Include only required headers into include/soc 3. Fill required FSP-M UPD to call FSP-M API 4. Ref: Processor EDS documents Panther Lake U/H 12Xe/H 4Xe External Design Specification (EDS) Rev. 0.7, vol 1 of 2 #815002 and Volume 2 of 2 #813030 BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848 Signed-off-by: Saurabh Mishra Reviewed-on: https://review.coreboot.org/c/coreboot/+/83635 Tested-by: build bot (Jenkins) Reviewed-by: Jamie Ryu Reviewed-by: Subrata Banik --- src/soc/intel/pantherlake/Kconfig | 96 +++++++++++++++++++++++++++++++++------ 1 file changed, 83 insertions(+), 13 deletions(-) (limited to 'src/soc/intel/pantherlake/Kconfig') diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index 179d2abe12..5e5516a4f4 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -6,22 +6,31 @@ config SOC_INTEL_PANTHERLAKE_BASE select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS + select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select FSP_M_XIP + select FSP_USES_CB_DEBUG_EVENT_HANDLER select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW select HAVE_X86_64_SUPPORT select IDT_IN_EVERY_STAGE + select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE + select IOAPIC select MICROCODE_BLOB_UNDISCLOSED + select MRC_SETTINGS_PROTECT select PLATFORM_USES_FSP2_4 select SOC_INTEL_COMMON select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_CAR + select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_IOE_P2SB + select SOC_INTEL_COMMON_BLOCK_MEMINIT select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET + select SOC_INTEL_IOE_DIE_SUPPORT select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER @@ -37,10 +46,20 @@ config SOC_INTEL_PANTHERLAKE_U_H bool select SOC_INTEL_PANTHERLAKE_BASE help - Choose this option if your mainboard has a PTL-UH SoC. + Choose this option if the mainboard is built using either a PTL-U (15W) or + PTL-H 12Xe (25W) system-on-a-chip SoC. Note, PTL U/H processor line is offered in a single package platform that includes the Compute tile, the PCD tile, and the GFX tile on the same package. +config SOC_INTEL_PANTHERLAKE_H + bool + depends on !SOC_INTEL_PANTHERLAKE_U_H + select SOC_INTEL_PANTHERLAKE_BASE + help + Choose this option if the mainboard is built using PTL-H 4Xe system-on-a-chip (SoC). + Note, PTL-H processor line is offered in a single package platform that includes the + Compute tile, the PCD tile, and the GFX tile on the same package. + if SOC_INTEL_PANTHERLAKE_BASE config CAR_ENHANCED_NEM @@ -89,6 +108,19 @@ config IED_REGION_SIZE hex default 0x400000 +config MAX_TBT_ROOT_PORTS + int + default 4 + +config MAX_ROOT_PORTS + int + default 10 if SOC_INTEL_PANTHERLAKE_H + default 12 + +config MAX_PCIE_CLOCK_SRC + int + default 9 + config PCR_BASE_ADDRESS hex default 0x4000000000 @@ -139,18 +171,6 @@ config SOC_INTEL_USB3_DEV_MAX int default 2 -config MAX_TBT_ROOT_PORTS - int - default 4 - -config MAX_ROOT_PORTS - int - default 12 - -config MAX_PCIE_CLOCK_SRC - int - default 9 - config CONSOLE_UART_BASE_ADDRESS hex default 0xfe02c000 @@ -194,4 +214,54 @@ config CONSOLE_CBMEM_BUFFER_SIZE default 0x100000 if BUILDING_WITH_DEBUG_FSP default 0x40000 +config FSP_HEADER_PATH + string "Location of FSP headers" + default "src/vendorcode/intel/fsp/fsp2_0/pantherlake/" + +config SOC_INTEL_PANTHERLAKE_DEBUG_CONSENT + int "Debug Consent" + # USB DBC is more common for developers so make this default to 4 if + # SOC_INTEL_DEBUG_CONSENT=y + default 4 if SOC_INTEL_DEBUG_CONSENT + default 0 + help + This is to control debug interface on SOC. + Setting non-zero value will allow to use DBC or DCI to debug SOC. + PlatformDebugConsent in FspmUpd.h has the details. + + Desired platform debug type are + 0:Disabled, + 2:Enabled Trace active: TraceHub is enabled and trace is active, + blocks s0ix, + 4:Enabled Trace ready: TraceHub is enabled and allowed S0ix, + 6:Enabled Trace power off: TraceHub is powergated, provide setting close to + functional low power state, + 7:user needs to configure Advanced Debug Settings manually. + +config DATA_BUS_WIDTH + int + default 128 + +config DIMMS_PER_CHANNEL + int + default 2 + +config MRC_CHANNEL_WIDTH + int + default 16 + +config BUILDING_WITH_DEBUG_FSP + bool "Debug FSP is used for the build" + default n + help + Set this option if debug build of FSP is used. + +config FSP_PUBLISH_MBP_HOB + bool + default n if CHROMEOS + default y + help + This is to control creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. + Disabling it for the platforms, which do not use MBP HOB, can improve the boot time. + endif -- cgit v1.2.3