From a35c0e81b6db65db82faf58386997111413cb687 Mon Sep 17 00:00:00 2001 From: Kapil Porwal Date: Thu, 25 Aug 2022 10:25:26 +0000 Subject: soc/intel/mtl: Hook up Lp5CccConfig FSP UPD Hook up Lp5CccConfig FSP UPD for Intel MeteorLake. BUG=b:243734885 TEST=Built and booted on Google Rex. Verified the UPD value in MRC log. Signed-off-by: Kapil Porwal Change-Id: I3d7ff8e08546f06cf7807ee825cfef84c14a6c5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/67052 Reviewed-by: Subrata Banik Reviewed-by: Maulik Vaghela Tested-by: build bot (Jenkins) Reviewed-by: Tarun Tuli Reviewed-by: Eric Lai --- src/soc/intel/meteorlake/meminit.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/meteorlake') diff --git a/src/soc/intel/meteorlake/meminit.c b/src/soc/intel/meteorlake/meminit.c index 4fdbdb209c..fa7e1fd09a 100644 --- a/src/soc/intel/meteorlake/meminit.c +++ b/src/soc/intel/meteorlake/meminit.c @@ -25,6 +25,7 @@ static void set_rcomp_config(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg) static void meminit_lp5x(FSP_M_CONFIG *mem_cfg, const struct mem_lp5x_config *lp5x_config) { mem_cfg->DqPinsInterleaved = 0; + mem_cfg->Lp5CccConfig = lp5x_config->ccc_config; } static void meminit_ddr(FSP_M_CONFIG *mem_cfg, const struct mem_ddr_config *ddr_config) -- cgit v1.2.3