From 31e0aeb74778a836636573952a40c847686ef69d Mon Sep 17 00:00:00 2001 From: Ravi Sarawadi Date: Wed, 12 Oct 2022 00:05:41 -0700 Subject: soc/intel/meteorlake: Increase pcie snoop/non-snoop latency MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes an issue where pcie was not power gating and blocked S0ix entry. Overwrite pcie max non-snoop and snoop latency tolerance values to 15.73ms as stated in doc #729123 - MTL External Design Specification. BUG=none TEST=Boot google/rex, print/check values. Signed-off-by: Ravi Sarawadi Change-Id: I9dfb9edbac95d28d50653777466ea172be64f612 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68308 Reviewed-by: Jérémy Compostella Tested-by: build bot (Jenkins) --- src/soc/intel/meteorlake/Kconfig | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src/soc/intel/meteorlake') diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index ee29b50849..311f636d1a 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -385,4 +385,16 @@ config DROP_CPU_FEATURE_PROGRAM_IN_FSP This feature is default enabled, in case of "coreboot running MP init" aka MP_SERVICES_PPI_V2_NOOP config is selected. +config PCIE_LTR_MAX_SNOOP_LATENCY + hex + default 0x100f + help + Latency tolerance reporting, max snoop latency value defaults to 15.73 ms. + +config PCIE_LTR_MAX_NO_SNOOP_LATENCY + hex + default 0x100f + help + Latency tolerance reporting, max non-snoop latency value defaults to 15.73 ms. + endif -- cgit v1.2.3