From 91ffac8c04776e1e663c5987ea718522f605a9b4 Mon Sep 17 00:00:00 2001
From: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Date: Sat, 7 May 2022 16:37:09 -0700
Subject: soc/intel/mtl: Do initial Meteor Lake SoC commit till ramstage

List of changes:
1. Add required SoC programming till ramstage
2. Include only required headers into include/soc
3. Fill required FSP-S UPD to call FSP-S API

BUG=b:224325352
TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'.

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Ie746c0bfcf1f315a4ab6f540cc7c4933157551d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63364
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/meteorlake/xhci.c | 39 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)
 create mode 100644 src/soc/intel/meteorlake/xhci.c

(limited to 'src/soc/intel/meteorlake/xhci.c')

diff --git a/src/soc/intel/meteorlake/xhci.c b/src/soc/intel/meteorlake/xhci.c
new file mode 100644
index 0000000000..9b4ac1b066
--- /dev/null
+++ b/src/soc/intel/meteorlake/xhci.c
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/pci_type.h>
+#include <intelblocks/xhci.h>
+#include <soc/pci_devs.h>
+
+#define XHCI_USB2_PORT_STATUS_REG	0x480
+#define XHCI_USB3_PORT_STATUS_REG	0x540
+#define XHCI_USB2_PORT_NUM		10
+#define XHCI_USB3_PORT_NUM		4
+
+#define TCSS_XHCI_USB2_PORT_STATUS_REG	0x480
+#define TCSS_XHCI_USB3_PORT_STATUS_REG	0x490
+#define TCSS_XHCI_USB2_PORT_NUM		0
+#define TCSS_XHCI_USB3_PORT_NUM		4
+
+static const struct xhci_usb_info usb_info = {
+	.usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG,
+	.num_usb2_ports = XHCI_USB2_PORT_NUM,
+	.usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG,
+	.num_usb3_ports = XHCI_USB3_PORT_NUM,
+};
+
+static const struct xhci_usb_info tcss_usb_info = {
+	.usb2_port_status_reg = TCSS_XHCI_USB2_PORT_STATUS_REG,
+	.num_usb2_ports = TCSS_XHCI_USB2_PORT_NUM,
+	.usb3_port_status_reg = TCSS_XHCI_USB3_PORT_STATUS_REG,
+	.num_usb3_ports = TCSS_XHCI_USB3_PORT_NUM,
+};
+
+const struct xhci_usb_info *soc_get_xhci_usb_info(pci_devfn_t xhci_dev)
+{
+	if (xhci_dev == PCI_DEVFN_XHCI)
+		return &usb_info;
+	else if (xhci_dev == PCI_DEVFN_TCSS_XHCI)
+		return &tcss_usb_info;
+
+	return NULL;
+}
-- 
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