From 82226f6e5c9a08ca9635ff9374346edc8d6cba1f Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 14 Jun 2023 23:43:08 +0530 Subject: =?UTF-8?q?soc/intel/meteorlake:=20Disable=C2=A0ACPI=20PM=20timer?= =?UTF-8?q?=20using=20IOE.PMC?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch disables the ACPI PM timer which is necessary for XTAL OSC shutdown. Also, disabling ACPI PM timer switches off TCO. BUG=b:274744845 TEST=Able to boot and verify S0ix is working even with EC reset and cold boot scenarios. w/o this cl: > iotools mmio_read32 0xfe4018fc 0x0 w/ this cl: > iotools mmio_read32 0xfe4018fc 0x2 Change-Id: Ibb6e145f67dba7270e0a322ef414bf1cb09c5eda Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/75822 Tested-by: build bot (Jenkins) Reviewed-by: Kapil Porwal --- src/soc/intel/meteorlake/include/soc/iomap.h | 3 +++ src/soc/intel/meteorlake/include/soc/pm.h | 3 +++ 2 files changed, 6 insertions(+) (limited to 'src/soc/intel/meteorlake/include') diff --git a/src/soc/intel/meteorlake/include/soc/iomap.h b/src/soc/intel/meteorlake/include/soc/iomap.h index a2df40ccb4..3efe400fa9 100644 --- a/src/soc/intel/meteorlake/include/soc/iomap.h +++ b/src/soc/intel/meteorlake/include/soc/iomap.h @@ -25,6 +25,9 @@ #define HPET_BASE_ADDRESS 0xfed00000 +#define IOE_PWRM_BASE_ADDRESS 0xfe400000 +#define IOE_PWRM_BASE_SIZE 0x10000 + #define PCH_PWRM_BASE_ADDRESS 0xfe000000 #define PCH_PWRM_BASE_SIZE 0x10000 diff --git a/src/soc/intel/meteorlake/include/soc/pm.h b/src/soc/intel/meteorlake/include/soc/pm.h index c486232e7d..7474cdd8bc 100644 --- a/src/soc/intel/meteorlake/include/soc/pm.h +++ b/src/soc/intel/meteorlake/include/soc/pm.h @@ -150,6 +150,9 @@ struct chipset_power_state { /* Get base address PMC memory mapped registers. */ uint8_t *pmc_mmio_regs(void); +/* Get base address IOE.PMC memory mapped registers. */ +uint8_t *ioe_pmc_mmio_regs(void); + /* Get base address of TCO I/O registers. */ uint16_t smbus_tco_regs(void); -- cgit v1.2.3