From 91ffac8c04776e1e663c5987ea718522f605a9b4 Mon Sep 17 00:00:00 2001
From: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Date: Sat, 7 May 2022 16:37:09 -0700
Subject: soc/intel/mtl: Do initial Meteor Lake SoC commit till ramstage

List of changes:
1. Add required SoC programming till ramstage
2. Include only required headers into include/soc
3. Fill required FSP-S UPD to call FSP-S API

BUG=b:224325352
TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'.

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Ie746c0bfcf1f315a4ab6f540cc7c4933157551d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63364
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/meteorlake/i2c.c | 43 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)
 create mode 100644 src/soc/intel/meteorlake/i2c.c

(limited to 'src/soc/intel/meteorlake/i2c.c')

diff --git a/src/soc/intel/meteorlake/i2c.c b/src/soc/intel/meteorlake/i2c.c
new file mode 100644
index 0000000000..50ab4a73eb
--- /dev/null
+++ b/src/soc/intel/meteorlake/i2c.c
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <drivers/i2c/designware/dw_i2c.h>
+#include <soc/pci_devs.h>
+
+int dw_i2c_soc_devfn_to_bus(unsigned int devfn)
+{
+	switch (devfn) {
+	case PCI_DEVFN_I2C0:
+		return 0;
+	case PCI_DEVFN_I2C1:
+		return 1;
+	case PCI_DEVFN_I2C2:
+		return 2;
+	case PCI_DEVFN_I2C3:
+		return 3;
+	case PCI_DEVFN_I2C4:
+		return 4;
+	case PCI_DEVFN_I2C5:
+		return 5;
+	}
+	return -1;
+}
+
+int dw_i2c_soc_bus_to_devfn(unsigned int bus)
+{
+	switch (bus) {
+	case 0:
+		return PCI_DEVFN_I2C0;
+	case 1:
+		return PCI_DEVFN_I2C1;
+	case 2:
+		return PCI_DEVFN_I2C2;
+	case 3:
+		return PCI_DEVFN_I2C3;
+	case 4:
+		return PCI_DEVFN_I2C4;
+	case 5:
+		return PCI_DEVFN_I2C5;
+	}
+	return -1;
+}
-- 
cgit v1.2.3