From eb80b1efa36c99e485b2604e913c2aa316168eea Mon Sep 17 00:00:00 2001 From: John Zhao Date: Wed, 3 Aug 2022 20:07:03 -0700 Subject: soc/intel/meteorlake: Provide access to IOE through P2SB SBI for TCSS This change provides access to IOE through P2SB Sideband interface for Meteor Lake TCSS functions of pad configuration and Thunderbolt authentication. There is a policy of locking the P2SB access at the end of platform initialization. The tbt_authentication is read from IOM register through IOE P2SB at early silicon initialization phase and its usage is deferred to usb4 driver. BUG=b:213574324 TEST=Built coreboot and validated booting to OS successfully on MTLRVP board. No boot hung was observed. Change-Id: Icd644c945bd293a8b9c4a364aaed99ec4a7c12f9 Signed-off-by: John Zhao Reviewed-on: https://review.coreboot.org/c/coreboot/+/66410 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Tarun Tuli --- src/soc/intel/meteorlake/chip.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/intel/meteorlake/chip.h') diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index 05d77f3d1c..04b8299b2d 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -126,6 +126,8 @@ struct soc_intel_meteorlake_config { /* Program OC pins for TCSS */ struct tcss_port_config tcss_ports[MAX_TYPE_C_PORTS]; uint8_t tbt_pcie_port_disable[4]; + /* Validate TBT firmware authenticated and loaded into IMR */ + bool tbt_authentication; /* SATA related */ uint8_t sata_mode; -- cgit v1.2.3