From 4866712b04a4fc6f1a72cd668de0ac91fc9a2a74 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sat, 16 Mar 2024 18:11:53 +0530 Subject: soc/intel/mtl: Enable RAMTOP caching at SoC level for MTL devices This patch enables the `SOC_INTEL_COMMON_BASECODE_RAMTOP` configuration at the SoC level for all MTL devices. This change streamlines the configuration process, avoiding redundant selections on individual mainboards. BUG=b:306677879 BRANCH=firmware-rex-15709.B TEST=Verified boot functionality on google/ovis and google/rex. Change-Id: I3aa3a83c190d0a0e93c267222a9dca0ac7651f9c Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/81271 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/intel/meteorlake/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/meteorlake/Kconfig') diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 43bb25ef25..a4ebad4706 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -84,7 +84,7 @@ config SOC_INTEL_METEORLAKE select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_BASECODE - select SOC_INTEL_COMMON_BASECODE_RAMTOP if !MAINBOARD_HAS_CHROMEOS + select SOC_INTEL_COMMON_BASECODE_RAMTOP select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET -- cgit v1.2.3