From e927d9b3adc9c5a4e4cc6757949f626458a80e68 Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Wed, 17 Jun 2020 17:35:25 +0530 Subject: soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init Since coreboot is initializing uart for debug logs, fsp should not reinitialize it. Thus we need to set FSP UPD to skip Uart init in FSP and use settings done by coreboot BUG=None BRANCH=None TEST=FSP is able to push debug logs on UART with this setting Cq-Depend: TBD Change-Id: I0fda2ace3b1f63159e9809d6a3044a3bad452f07 Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/42462 Tested-by: build bot (Jenkins) Reviewed-by: Ronak Kanabar --- src/soc/intel/jasperlake/romstage/fsp_params.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/jasperlake') diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c index d9063b0b0c..6d4055ab51 100644 --- a/src/soc/intel/jasperlake/romstage/fsp_params.c +++ b/src/soc/intel/jasperlake/romstage/fsp_params.c @@ -81,6 +81,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->VtdDisable = 0; m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; + m_cfg->SerialIoUartDebugMode = config->SerialIoUartMode[CONFIG_UART_FOR_CONSOLE]; /* Display */ m_cfg->DdiPortAConfig = config->DdiPortAConfig; -- cgit v1.2.3