From d8b4ea992b0c1481f5aed0adfee9b8f28273f5db Mon Sep 17 00:00:00 2001 From: Sumeet R Pawnikar Date: Tue, 26 May 2020 19:59:45 +0530 Subject: soc/intel/jasperlake: add processor power limits control support Add processor power limits control support to configure values for jasperlake soc based platforms. BRANCH=None BUG=None TEST=Built for dedede system Change-Id: Ib5502b225c1158c1f0729ce799ed0b8101f0233f Signed-off-by: Sumeet R Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/41777 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/jasperlake/systemagent.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'src/soc/intel/jasperlake') diff --git a/src/soc/intel/jasperlake/systemagent.c b/src/soc/intel/jasperlake/systemagent.c index 072db796a8..080446c507 100644 --- a/src/soc/intel/jasperlake/systemagent.c +++ b/src/soc/intel/jasperlake/systemagent.c @@ -1,10 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include +#include #include +#include #include /* @@ -43,9 +46,17 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) */ void soc_systemagent_init(struct device *dev) { + struct soc_power_limits_config *soc_config; + config_t *config; + /* Enable Power Aware Interrupt Routing */ enable_power_aware_intr(); /* Enable BIOS Reset CPL */ enable_bios_reset_cpl(); + + mdelay(1); + config = config_of_soc(); + soc_config = &config->power_limits_config; + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); } -- cgit v1.2.3