From 69589294c205b616e80cafbbfb0b33e105a75386 Mon Sep 17 00:00:00 2001
From: Ronak Kanabar <ronak.kanabar@intel.com>
Date: Wed, 27 May 2020 11:25:45 +0530
Subject: soc/intel/jasperlake: Disable PAVP UPD

This patch will disable PAVP UPD, which is by default enabled in FSP.

BUG=b:155595624
BRANCH=None
TEST=Build, boot JSLRVP, Verified UPD values from FSP log

Change-Id: I8e103ad11ae6ffa6b9efe4bf249bbe344bc10a30
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41763
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/jasperlake/fsp_params.c | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/soc/intel/jasperlake')

diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index eafc374584..75e1c64513 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -210,6 +210,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 		params->XdciEnable = 0;
 	}
 
+	/* Disable Pavp */
+	params->PavpEnable = 0;
+
 	/* Provide correct UART number for FSP debug logs */
 	params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
 
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