From 4742f537705e1b3a97dd737bb8a1fc13fc89f7f7 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Mon, 22 Feb 2021 15:13:05 +0530 Subject: soc/intel/{adl,jsl,ehl,tgl}: Remove ITSS polarity restore Post boot SAI PCR access to ITSS polarity regsiter is locked. Restore of ITSS polarity does not take effect anyways. Hence removing the related programming. Change-Id: I1adab45ee903b9d9c1d98a060143445c0cee0968 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/51002 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Tim Wawrzynczak --- src/soc/intel/jasperlake/chip.c | 7 ------- 1 file changed, 7 deletions(-) (limited to 'src/soc/intel/jasperlake') diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c index ce4004db89..c663d1f5e7 100644 --- a/src/soc/intel/jasperlake/chip.c +++ b/src/soc/intel/jasperlake/chip.c @@ -122,19 +122,12 @@ static void soc_fill_gpio_pm_configuration(void) void soc_init_pre_device(void *chip_info) { - /* Snapshot the current GPIO IRQ polarities. FSP is setting a - * default policy that doesn't honor boards' requirements. */ - itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - /* Perform silicon specific init. */ fsp_silicon_init(); /* Display FIRMWARE_VERSION_INFO_HOB */ fsp_display_fvi_version_hob(); - /* Restore GPIO IRQ polarities back to previous settings. */ - itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - soc_fill_gpio_pm_configuration(); /* swap enabled PCI ports in device tree if needed */ -- cgit v1.2.3