From 0e905801f8ff6c10b20625e31d851920b3f4c4f2 Mon Sep 17 00:00:00 2001 From: Michael Niewöhner Date: Sat, 25 Sep 2021 00:10:30 +0200 Subject: soc/intel: transition full control over PM Timer from FSP to coreboot MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set `EnableTcoTimer=1` in order to keep FSP from 1) enabling ACPI Timer emulation in uCode. 2) disabling the PM ACPI Timer. Both actions are now done in coreboot. `EnableTcoTimer=1` makes FSP skip these steps in any possible case including `SkipMpInit=0`, `SkipMpInit=1`, use of the MP PPI or FSP Multiphase Init. This way full control is left to coreboot. Change-Id: I8005daed732c031980ccc379375ff5b09df8dac1 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/57933 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Lance Zhao --- src/soc/intel/jasperlake/fsp_params.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/soc/intel/jasperlake') diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 18db9359ce..085148f7b3 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -85,6 +85,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->Enable8254ClockGating = !use_8254; params->Enable8254ClockGatingOnS3 = 1; + /* + * Legacy PM ACPI Timer (and TCO Timer) + * This *must* be 1 in any case to keep FSP from + * 1) enabling PM ACPI Timer emulation in uCode. + * 2) disabling the PM ACPI Timer. + * We handle both by ourself! + */ + params->EnableTcoTimer = 1; + /* disable Legacy PME */ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); -- cgit v1.2.3