From 830306cc84bc909e7484a9568a7475f89987f857 Mon Sep 17 00:00:00 2001 From: Krishna Prasad Bhat Date: Wed, 30 Dec 2020 14:01:40 +0530 Subject: soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification USBSUSPGQDIS is a disqualifier bit which will allow platform to enter s0ix even if USB2 PHY SUS is not power gated. Disabling this bit will ensure that USB2 PHY SUS is power gated before entering s0ix. BUG=b:175767084 BRANCH=dedede TEST=s0ix works on drawcia and USB wake from s0ix works fine. Change-Id: I20bad3f79141799c88a16272ea822b9e3dede504 Signed-off-by: Krishna Prasad Bhat Reviewed-on: https://review.coreboot.org/c/coreboot/+/49012 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Karthik Ramasubramanian Reviewed-by: Evan Green --- src/soc/intel/jasperlake/finalize.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'src/soc/intel/jasperlake/finalize.c') diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c index d879db94fc..8219f0c1d5 100644 --- a/src/soc/intel/jasperlake/finalize.c +++ b/src/soc/intel/jasperlake/finalize.c @@ -40,6 +40,8 @@ static void pch_handle_sideband(config_t *config) static void pch_finalize(void) { + uint32_t reg32; + uint8_t *pmcbase; config_t *config; /* TCO Lock down */ @@ -62,6 +64,17 @@ static void pch_finalize(void) if (config->PmTimerDisabled) pmc_disable_acpi_timer(); + pmcbase = pmc_mmio_regs(); + if (config->s0ix_enable) { + /* + * Enable USBSUSPGQDIS qualification to ensure USB2 PHY SUS is power gated + * before entering s0ix. + */ + reg32 = read32(pmcbase + CPPMVRIC3); + reg32 &= ~USBSUSPGQDIS; + write32(pmcbase + CPPMVRIC3, reg32); + } + pch_handle_sideband(config); pmc_clear_pmcon_sts(); -- cgit v1.2.3