From c47422d6c3970baee5da2a9085a70bf3f987fcd5 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Mon, 1 Jun 2020 17:03:41 -0600 Subject: soc/intel/jasperlake: Add JSL PMC as 'hidden' PCI device This change allows treating the PMC as a 'hidden' PCI device on Jasper Lake, so that the MMIO & I/O resources can be exposed as belonging to this device, instead of the system agent and LPC/eSPI. Change-Id: Ie07987c68388d03359c43f64a849dc6e3f94676e Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/42018 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/jasperlake/espi.c | 17 ----------------- 1 file changed, 17 deletions(-) (limited to 'src/soc/intel/jasperlake/espi.c') diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c index 7acd0a0417..a1954fd414 100644 --- a/src/soc/intel/jasperlake/espi.c +++ b/src/soc/intel/jasperlake/espi.c @@ -191,21 +191,4 @@ void lpc_soc_init(struct device *dev) soc_mirror_dmi_pcr_io_dec(); } -/* Fill up ESPI IO resource structure inside SoC directory */ -void pch_lpc_soc_fill_io_resources(struct device *dev) -{ - /* - * PMC pci device gets hidden from PCI bus due to Silicon - * policy hence bind ACPI BASE aka ABASE (offset 0x20) with - * ESPI IO resources to ensure that ABASE falls under PCI reserved - * IO memory range. - * - * Note: Don't add any more resource with same offset 0x20 - * under this device space. - */ - pch_lpc_add_new_resource(dev, PCI_BASE_ADDRESS_4, - ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, IORESOURCE_IO | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED); -} - #endif -- cgit v1.2.3