From 512b77abb582e6c2566d3873b273dd32731e7bae Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Wed, 25 Mar 2020 13:20:34 +0530 Subject: soc/intel/jasperlake: Remove Tiger Lake SoC code from Jasper Lake This is a follow-up patch to initial copy patch for Jasper Lake SoC. Remove all Tiger Lake specfic code from Jasper Lake SoC code. BUG=b:150217037 Change-Id: I44dc6bf55ca18a3f0c350f5c3e9fae2996958648 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/39824 Reviewed-by: Furquan Shaikh Reviewed-by: Karthik Ramasubramanian Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/jasperlake/acpi/pmc.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/jasperlake/acpi/pmc.asl') diff --git a/src/soc/intel/jasperlake/acpi/pmc.asl b/src/soc/intel/jasperlake/acpi/pmc.asl index 6dd2d35354..0e3e24d94e 100644 --- a/src/soc/intel/jasperlake/acpi/pmc.asl +++ b/src/soc/intel/jasperlake/acpi/pmc.asl @@ -19,7 +19,7 @@ Scope (\_SB.PCI0) { Device (PMC) { Name (_HID, "INTC1026") - Name (_DDN, "Intel(R) Tiger Lake IPC Controller") + Name (_DDN, "Intel(R) Jasper Lake IPC Controller") /* * PCH preserved 32 MB MMIO range from 0xFC800000 to 0xFE7FFFFF. * 64KB (0xFE000000 - 0xFE00FFFF) for PMC MBAR. -- cgit v1.2.3