From 4225a796fa44efa372e398ce05d3eca3d819ed6e Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 19 Dec 2022 18:24:13 +0530
Subject: soc/intel/{apl,cnl,jsl}: Enable EISA HID support for DPTF

This patch selects `HAVE_DPTF_EISA_HID` config for APL, CNL and JSL
platform.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ice01c5720ba7f15861899d89981225cb76f9fcd5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71109
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
---
 src/soc/intel/jasperlake/Kconfig | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/soc/intel/jasperlake/Kconfig')

diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index 183657445d..4ae21b87e4 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -21,6 +21,7 @@ config CPU_SPECIFIC_OPTIONS
 	select FSP_M_XIP
 	select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
 	select GENERIC_GPIO_LIB
+	select HAVE_DPTF_EISA_HID
 	select HAVE_FSP_GOP
 	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select HAVE_SMI_HANDLER
-- 
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