From 6a9d2f989975a63f569750113aa3b88255fb2bea Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 28 Mar 2019 10:07:15 +0530 Subject: soc/intel/icelake: Fix chipset_power_state structure This patch ports CB:30717 changes from CNL to ICL. This structure is declared as a static CAR_GLOBAL in the common PMC library code and in the SOC specific code. Remove the SOC specific version and instead get the chipset_power_state pointer from the PMC library. This fixes events that were recorded in chipset_power_state at boot but were reading as all zero when it was time to parse the structure when logging events to flash. Change-Id: I1152d0e882e1acf475072d1553b74f9161e2f485 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/32095 Reviewed-by: Furquan Shaikh Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/soc/intel/icelake/romstage/romstage.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'src/soc/intel/icelake') diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 92fb1e4647..a61370a1ee 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -31,8 +31,6 @@ #include #include -static struct chipset_power_state power_state; - #define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ @@ -111,7 +109,7 @@ asmlinkage void car_stage_entry(void) bool s3wake; struct postcar_frame pcf; uintptr_t top_of_ram; - struct chipset_power_state *ps = &power_state; + struct chipset_power_state *ps = pmc_get_power_state(); console_init(); -- cgit v1.2.3