From 14d59912f8cdbec7e0121042c43e5728dc361509 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 1 Nov 2019 15:44:17 +0530 Subject: soc/intel/icelake: Add alignment check for TSEG base and size This patch ensures to not set SMRR if TSEG base is not align with TSEG size Change-Id: I77d1cb2fd287f45859cde37a564ea7c147d5633f Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/36542 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/soc/intel/icelake/smmrelocate.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/soc/intel/icelake/smmrelocate.c') diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index edcc49db5e..8f56ad6650 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -178,6 +178,13 @@ static void fill_in_relocation_params(struct smm_relocation_params *params) const u32 rmask = ~(4 * KiB - 1); smm_region(&tseg_base, &tseg_size); + + if (!IS_ALIGNED(tseg_base, tseg_size)) { + printk(BIOS_WARNING, + "TSEG base not aligned with TSEG SIZE! Not setting SMRR\n"); + return; + } + smm_subregion(SMM_SUBREGION_CHIPSET, ¶ms->ied_base, ¶ms->ied_size); /* SMRR has 32-bits of valid address aligned to 4KiB. */ -- cgit v1.2.3