From 1b1a26acdc814d0478bb5fda0b6664076a60fdf1 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 5 Nov 2019 16:54:58 +0530 Subject: soc/intel/icelake: Refactor pch_early_init() code This patch keeps required pch_early_init() function like ABASE programming, GPE and RTC init into bootblock and moves remaining functions like TCO configuration and SMBUS init into romstage/pch.c in order to maintain only required chipset programming for bootblock and verstage. TEST=Able to build and boot ICL DE system. Change-Id: I4f0914242c3215f6bf76e41c468f544361a740d8 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/36627 Reviewed-by: Aamir Bohra Reviewed-by: Furquan Shaikh Reviewed-by: Maulik V Vaghela Tested-by: build bot (Jenkins) --- src/soc/intel/icelake/romstage/pch.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 src/soc/intel/icelake/romstage/pch.c (limited to 'src/soc/intel/icelake/romstage/pch.c') diff --git a/src/soc/intel/icelake/romstage/pch.c b/src/soc/intel/icelake/romstage/pch.c new file mode 100644 index 0000000000..88a7cc7163 --- /dev/null +++ b/src/soc/intel/icelake/romstage/pch.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +void pch_init(void) +{ + /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ + tco_configure(); + + /* Program SMBUS_BASE_ADDRESS and Enable it */ + smbus_common_init(); +} -- cgit v1.2.3