From 0e3c245c6cf4b8fe415c3309098cd51795d90fcf Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 10 Sep 2019 16:00:08 +0530 Subject: soc/intel/{cnl, icl}: Cache the TSEG region MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch helps to save additional ~19ms of booting time in normal boot and s3 resume on CML-hatch. BUG=b:140008206 TEST=Verified normal boot time on CML-Hatch with latest coreboot Without this CL: Total Time: 929ms With this CL: (TSEG marked as WB) Total Time: 910ms For test marked TSEG as WP/WC: Total Time: ~920ms Change-Id: Ie92d2c9e50fa299db1cd8c57a6047ea3adaf1452 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/35026 Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/soc/intel/icelake/memmap.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/icelake/memmap.c') diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 71368c645a..20c4e6fb7d 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -278,4 +278,7 @@ void fill_postcar_frame(struct postcar_frame *pcf) printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); top_of_ram -= 16*MiB; postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); + + /* Cache the TSEG region */ + postcar_enable_tseg_cache(pcf); } -- cgit v1.2.3