From b6df6b065cffea9b93f6fdbd041ee15e4ec6fd61 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 3 Jan 2020 15:29:02 +0530 Subject: soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper This patch ensures coreboot is not publishing above 4GB mmio resource if soc common config "enable_above_4GB_mmio" not enable. Publishing unnecessary 4GB above MMIO resource with wrong base and size is causing problem while working with discrete GPU. Unable to boot with dGPU on IA platform with below error: [ 2.297425] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.302858] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.309427] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.316679] pcieport 0000:00:1c.0: bridge window [mem 0x840000000-0x8c01fffff 64bit pref] [ 2.325072] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.330502] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.337062] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.344317] pcieport 0000:00:1c.0: bridge window [mem 0xa0000000-0xb01fffff 64bit pref] [ 2.352541] [drm] Not enough PCI address space for a large BAR. Change-Id: I77b3a0e44582b047d7fbe679d3000d616f7e6111 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/38125 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi Reviewed-by: Pratikkumar V Prajapati --- src/soc/intel/icelake/include/soc/iomap.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/icelake/include') diff --git a/src/soc/intel/icelake/include/soc/iomap.h b/src/soc/intel/icelake/include/soc/iomap.h index 218b8bfa60..50ba00561d 100644 --- a/src/soc/intel/icelake/include/soc/iomap.h +++ b/src/soc/intel/icelake/include/soc/iomap.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. + * Copyright (C) 2018-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -60,6 +60,10 @@ #define VTD_BASE_ADDRESS 0xFED90000 #define VTD_BASE_SIZE 0x00004000 + +#define ABOVE_4GB_MEM_BASE_ADDRESS (256ULL * GiB) +#define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB) + /* * I/O port address space */ -- cgit v1.2.3