From 9fe5dde68d8f07a1f78785f48fc39e6acdc98e6b Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 12 Jul 2019 18:32:55 +0530 Subject: soc/intel/icelake: Update FSP UPDs if IGD is disable in devicetree This patch sets required FSP UPDs to skip IGD initialziation if devicetree has disable IGD. Change-Id: I34a02bff112f922cabd48c23bc76370892ec62d9 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/33739 Reviewed-by: Furquan Shaikh Reviewed-by: Aamir Bohra Reviewed-by: Wonkyu Kim Tested-by: build bot (Jenkins) --- src/soc/intel/icelake/fsp_params.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) (limited to 'src/soc/intel/icelake/fsp_params.c') diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 03b00d94fb..382b1843f4 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -80,9 +80,20 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) mainboard_silicon_init_params(params); - params->PeiGraphicsPeimInit = 1; - params->GtFreqMax = 2; - params->CdClock = 3; + dev = pcidev_path_on_root(SA_DEVFN_IGD); + + if (!dev || !dev->enabled) { + /* + * Skip IGD initialization in FSP in case device is disabled + * in the devicetree.cb. + */ + params->PeiGraphicsPeimInit = 0; + } else { + params->PeiGraphicsPeimInit = 1; + params->GtFreqMax = 2; + params->CdClock = 3; + } + /* Unlock upper 8 bytes of RTC RAM */ params->PchLockDownRtcMemoryLock = 0; -- cgit v1.2.3