From 9d667906f3c0029dbea41580a0d0961cf1ab2fc9 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 19 Feb 2020 19:09:06 +0530 Subject: soc/intel/icelake: Skip FSP-S IGD related UPD override Default FSP values for "GtFreqMax" and "CdClock" UPDs are "Auto", hence related FSP-S UPD override can be avoided from coreboot. As per FSP-S UPD Header (FspsUpd.h) /** Offset 0x020E - GT Frequency Limit 0xFF: Auto(Default) **/ UINT8 GtFreqMax; /** Offset 0x0209 - CdClock Frequency selection 0: (Default) Auto **/ UINT8 CdClock; TEST=Able to get Pre-OS display on ICLRVP and Dragonegg platform. Change-Id: Ie500dd5fad5cd358ea3fad4d5c0be1b0c148584b Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/38992 Tested-by: build bot (Jenkins) Reviewed-by: V Sowmya --- src/soc/intel/icelake/fsp_params.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'src/soc/intel/icelake/fsp_params.c') diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 448b82c7d8..7514be107d 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -96,10 +96,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PeiGraphicsPeimInit = 1; else params->PeiGraphicsPeimInit = 0; - if (dev && dev->enabled) { - params->GtFreqMax = 2; - params->CdClock = 3; - } /* Unlock upper 8 bytes of RTC RAM */ params->PchLockDownRtcMemoryLock = 0; -- cgit v1.2.3