From 3d152ac388fa43b4c3d1bfeedcb6a40f1479ace3 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 31 Oct 2018 23:08:14 +0530 Subject: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS As per Icelake EDS PCI device B:D:F (0:0x1f:0) referred as ESPI, hence modify SoC code to reflect the same. This patch replaces all SoC specific PCI LPC references with ESPI except anything that touches intel common code block. Change-Id: I4990ea6d9b7b4c0eac2b3eea559f5469f086e827 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/33190 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Lean Sheng Tan --- src/soc/intel/icelake/fsp_params.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/icelake/fsp_params.c') diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 127507b45a..ac7edd2dbb 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -102,7 +102,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } /* Lan */ - dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 6); + dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 6); if (!dev) params->PchLanEnable = 0; else -- cgit v1.2.3