From 9df0440c6cd0031c81d15ed10df68a94fc43bac6 Mon Sep 17 00:00:00 2001
From: Aamir Bohra <aamir.bohra@intel.com>
Date: Thu, 22 Nov 2018 16:26:18 +0530
Subject: soc/intel/icelake: Add support to enable/disable USB charging in
 s3/S5

Change-Id: I0559b8a546f7a67759377c7f51b2faa2280aa797
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/29793
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/icelake/acpi/globalnvs.asl | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

(limited to 'src/soc/intel/icelake/acpi')

diff --git a/src/soc/intel/icelake/acpi/globalnvs.asl b/src/soc/intel/icelake/acpi/globalnvs.asl
index 678ce5ac23..b8f4d2fff6 100644
--- a/src/soc/intel/icelake/acpi/globalnvs.asl
+++ b/src/soc/intel/icelake/acpi/globalnvs.asl
@@ -48,8 +48,34 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	U2WE,	16,	// 0x2b - 0x2c USB2 Wake Enable Bitmap
 	U3WE,	16,	// 0x2d - 0x2e USB3 Wake Enable Bitmap
 	UIOR,	8,	// 0x2f - UART debug controller init on S3 resume
+	S5U0,	8,	// 0x30 - Enable USB in S5
+	S3U0,	8,	// 0x31 - Enable USB in S3
 
 	/* ChromeOS specific */
 	Offset (0x100),
 	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
 }
+
+/* Set flag to enable USB charging in S3 */
+Method (S3UE)
+{
+	Store (One, \S3U0)
+}
+
+/* Set flag to disable USB charging in S3 */
+Method (S3UD)
+{
+	Store (Zero, \S3U0)
+}
+
+/* Set flag to enable USB charging in S5 */
+Method (S5UE)
+{
+	Store (One, \S5U0)
+}
+
+/* Set flag to disable USB charging in S5 */
+Method (S5UD)
+{
+	Store (Zero, \S5U0)
+}
-- 
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