From 87c7ec7c0677ec5fda4a9cebb95c06edb23a96ba Mon Sep 17 00:00:00 2001 From: Shreesh Chhabbi Date: Thu, 3 Dec 2020 14:07:15 -0800 Subject: soc/intel: Remove INTEL_CAR_NEM_ENHANCED_V2 config option SF Mask MSRs' Programming which was done under this config selection will be moved under a new config option called CAR_HAS_SF_MASKS. This segregates the eNEM programming sequence based on sub features supported in each processor. Bug=b:171601324 BRANCH=volteer Test=Build volteer build and boot on Delbin EVT. Change-Id: If4d8d1ec52b7b79965fe1a957c48f571ec56dc63 Signed-off-by: Shreesh Chhabbi Reviewed-on: https://review.coreboot.org/c/coreboot/+/48284 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/icelake/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/icelake/Kconfig') diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 52e9a745f8..fee52e63a8 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -23,6 +23,7 @@ config CPU_SPECIFIC_OPTIONS select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE + select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC @@ -64,7 +65,6 @@ config CPU_SPECIFIC_OPTIONS select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI - select USE_CAR_NEM_ENHANCED_V1 config DCACHE_RAM_BASE default 0xfef00000 -- cgit v1.2.3