From ffcd9393a41e20883c219a2f47a1510aef82dcd4 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Mon, 7 Dec 2015 16:50:47 -0700 Subject: soc/intel/fsp_baytrail: Adjust root port INT routing Adjust the root port INT routing based on Bay Trail spec: Document Number: 538136, Rev. 3.9 Table 241. Interrupt Generated for INT[A-D] Interrupts INTA INTB INTC INTD Root Port 1 INTA# INTB# INTC# INTD# Root Port 2 INTD# INTA# INTB# INTC# Root Port 3 INTC# INTD# INTA# INTB# Root Port 4 INTB# INTC# INTD# INTA# Change-Id: I22a8c0bc6ad731dfb79385d6e165f1ec0a07507d Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/12684 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh Reviewed-by: Ben Gardner --- src/soc/intel/fsp_baytrail/southcluster.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/soc/intel/fsp_baytrail') diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index 3ad692fb2a..f493d2b07d 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -208,6 +208,16 @@ static void write_pci_config_irqs(void) if (targ_dev == NULL || new_int_pin < 1) continue; + /* + * Adjust the INT routing for the PCIe root ports + * See 'Interrupt Generated for INT[A-D] Interrupts' + * Table 241 in Document Number: 538136, Rev. 3.9 + */ + if (PCI_SLOT(targ_dev->path.pci.devfn) == PCIE_DEV && + targ_dev != irq_dev) + new_int_pin = ((new_int_pin - 1 + + PCI_FUNC(targ_dev->path.pci.devfn)) % 4) + 1; + /* Get the original INT_PIN for record keeping */ original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); -- cgit v1.2.3