From faf20d30a6e451d45e29613e3f4603dc72771843 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 14 Aug 2019 05:41:41 +0300 Subject: soc/intel: Rename some SMM support functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename southbridge_smm_X to smm_southbridge_X. Rename most southcluster_smm_X to smm_southbridge_X. Change-Id: I4f6f9207ba32cf51d75b9ca9230e38310a33a311 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34856 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/fsp_baytrail/cpu.c | 7 ++++--- src/soc/intel/fsp_baytrail/gpio.c | 3 +-- src/soc/intel/fsp_baytrail/include/soc/gpio.h | 1 + src/soc/intel/fsp_baytrail/include/soc/smm.h | 7 ------- src/soc/intel/fsp_baytrail/smm.c | 15 ++++++++------- 5 files changed, 14 insertions(+), 19 deletions(-) (limited to 'src/soc/intel/fsp_baytrail') diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index 769f4d4d76..7fe8f70581 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -17,7 +17,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -25,7 +27,6 @@ #include #include #include -#include #include #include @@ -152,7 +153,7 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase, static void enable_smis(void) { if (CONFIG(HAVE_SMI_HANDLER)) - southcluster_smm_enable_smi(); + smm_southbridge_enable_smi(); } static const struct mp_ops mp_ops = { @@ -160,7 +161,7 @@ static const struct mp_ops mp_ops = { .get_cpu_count = get_cpu_count, .get_smm_info = get_smm_info, .get_microcode_info = get_microcode_info, - .pre_mp_smm_init = southcluster_smm_clear_state, + .pre_mp_smm_init = smm_southbridge_clear_state, .relocation_handler = relocation_handler, .post_mp_init = enable_smis, }; diff --git a/src/soc/intel/fsp_baytrail/gpio.c b/src/soc/intel/fsp_baytrail/gpio.c index 2409eaa541..6da1258bf3 100644 --- a/src/soc/intel/fsp_baytrail/gpio.c +++ b/src/soc/intel/fsp_baytrail/gpio.c @@ -19,7 +19,6 @@ #include #include #include -#include /* * GPIO-to-Pad LUTs @@ -211,7 +210,7 @@ static void setup_gpio_route(const struct soc_gpio_map *sus, } } - southcluster_smm_save_gpio_route(route_reg); + smm_southcluster_save_gpio_route(route_reg); } static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS], diff --git a/src/soc/intel/fsp_baytrail/include/soc/gpio.h b/src/soc/intel/fsp_baytrail/include/soc/gpio.h index 3549894287..68c62350ce 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/gpio.h +++ b/src/soc/intel/fsp_baytrail/include/soc/gpio.h @@ -349,6 +349,7 @@ struct gpio_bank { const u8 gpio_f1_range_end; }; +void smm_southcluster_save_gpio_route(uint32_t route); void setup_soc_gpios(struct soc_gpio_config *config); /* This function is weak and can be overridden by a mainboard function. */ struct soc_gpio_config* mainboard_get_gpios(void); diff --git a/src/soc/intel/fsp_baytrail/include/soc/smm.h b/src/soc/intel/fsp_baytrail/include/soc/smm.h index c929572dbc..2ae7f5b08c 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/smm.h +++ b/src/soc/intel/fsp_baytrail/include/soc/smm.h @@ -30,11 +30,4 @@ static inline int smm_region_size(void) uintptr_t smm_region_start(void); -#if !defined(__PRE_RAM__) && !defined(__SMM___) -#include -void southcluster_smm_clear_state(void); -void southcluster_smm_enable_smi(void); -void southcluster_smm_save_gpio_route(uint32_t route); -#endif - #endif /* _BAYTRAIL_SMM_H_ */ diff --git a/src/soc/intel/fsp_baytrail/smm.c b/src/soc/intel/fsp_baytrail/smm.c index df55433314..0c40429aae 100644 --- a/src/soc/intel/fsp_baytrail/smm.c +++ b/src/soc/intel/fsp_baytrail/smm.c @@ -20,21 +20,22 @@ #include #include #include +#include #include +#include #include #include -#include /* Save the gpio route register. The settings are committed from - * southcluster_smm_enable_smi(). */ + * smm_southbridge_enable_smi(). */ static uint32_t gpio_route; -void southcluster_smm_save_gpio_route(uint32_t route) +void smm_southcluster_save_gpio_route(uint32_t route) { gpio_route = route; } -void southcluster_smm_clear_state(void) +void smm_southbridge_clear_state(void) { uint32_t smi_en; @@ -59,7 +60,7 @@ void southcluster_smm_clear_state(void) clear_pmc_status(); } -static void southcluster_smm_route_gpios(void) +static void smm_southcluster_route_gpios(void) { u32 *gpio_rout = (u32 *)(PMC_BASE_ADDRESS + GPIO_ROUT); const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI; @@ -84,7 +85,7 @@ static void southcluster_smm_route_gpios(void) outl(alt_gpio_reg, alt_gpio_smi); } -void southcluster_smm_enable_smi(void) +void smm_southbridge_enable_smi(void) { printk(BIOS_DEBUG, "Enabling SMIs.\n"); @@ -93,7 +94,7 @@ void southcluster_smm_enable_smi(void) disable_gpe(PME_B0_EN); /* Set up the GPIO route. */ - southcluster_smm_route_gpios(); + smm_southcluster_route_gpios(); /* Enable SMI generation: * - on APMC writes (io 0xb2) -- cgit v1.2.3