From 15588b03b36aa875e2a2a31cc649a2d9dff7581e Mon Sep 17 00:00:00 2001 From: Keith Short Date: Thu, 9 May 2019 11:40:34 -0600 Subject: post_code: add post code for hardware initialization failure Add a new post code POST_HW_INIT_FAILURE, used when coreboot fails to detect or initialize a required hardware component. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: I73820d24b3e1c269d9d446a78ef4f97e167e3552 Signed-off-by: Keith Short Reviewed-on: https://review.coreboot.org/c/coreboot/+/32774 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/soc/intel/fsp_baytrail/southcluster.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/fsp_baytrail/southcluster.c') diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index c84f4083d4..356b855f3b 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -98,7 +98,7 @@ static void sc_enable_ioapic(struct device *dev) reg32 = *ioapic_data; printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); if (reg32 != (1 << 25)) - die("APIC Error\n"); + die_with_post_code(POST_HW_INIT_FAILURE, "APIC Error\n"); printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); for (i=0; i<3; i++) { -- cgit v1.2.3