From f226a4d41db5ab314200206e7cb8731f022a14a6 Mon Sep 17 00:00:00 2001 From: York Yang Date: Tue, 7 Jul 2015 11:09:02 -0700 Subject: intel/fsp_baytrail: Support Baytrail FSP Gold4 release Baytrail FSP Gold4 release added 5 PCD options. Update UPD_DATA_REGION structure to include these new PCD options and initialized the setting when given in devicetree.cb. Change-Id: Ic343e79479464972455e42f9352b3bb116c6f80f Signed-off-by: York Yang Reviewed-on: http://review.coreboot.org/10838 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) mode change 100644 => 100755 src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c (limited to 'src/soc/intel/fsp_baytrail/fsp') diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c old mode 100644 new mode 100755 index 0abab98c7c..ad85c5b8a5 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2014 Intel Corporation + * Copyright (C) 2014-2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -112,6 +112,11 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U UPD_DEFAULT_CHECK(PcdSccEnablePciMode); UPD_DEFAULT_CHECK(IgdRenderStandby); UPD_DEFAULT_CHECK(TxeUmaEnable); + UPD_DEFAULT_CHECK(PcdOsSelection); + UPD_DEFAULT_CHECK(PcdEMMC45DDR50Enabled); + UPD_DEFAULT_CHECK(PcdEMMC45HS200Enabled); + UPD_DEFAULT_CHECK(PcdEMMC45RetuneTimerValue); + UPD_DEFAULT_CHECK(PcdEnableIgd); if ((config->PcdeMMCBootMode != EMMC_USE_DEFAULT) || (config->PcdeMMCBootMode != EMMC_FOLLOWS_DEVICETREE)) -- cgit v1.2.3