From 6b0933adf71fc5ce234e9fd924839b6759d06d7c Mon Sep 17 00:00:00 2001 From: David Imhoff Date: Wed, 6 May 2015 21:42:37 +0200 Subject: intel/fsp_baytrail: Fix logging of ISPEnable option Before this fix the value of PcdEnableSdio was printed as the MIPI/ISP configuration option. TEST=Built and booted on Minnowboard Max Change-Id: Ia9b02d520f4e615f90b45935456b9d97c5d00f11 Signed-off-by: David Imhoff Reviewed-on: http://review.coreboot.org/10126 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Werner Zeh --- src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/fsp_baytrail/fsp') diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index ad85c5b8a5..7e17f62811 100755 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -173,14 +173,14 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U if (FspInfo->ImageRevision >= FSP_GOLD3_REV_ID) { UpdData->ISPEnable = dev->enabled; } else { - /* Gold2 and earlier FSP: ISPEnable is the filed */ + /* Gold2 and earlier FSP: ISPEnable is the field */ /* next to PcdGttSize in UPD_DATA_REGION struct */ *(&(UpdData->PcdGttSize)+sizeof(UINT8)) = dev->enabled; printk (FSP_INFO_LEVEL, "Baytrail Gold2 or earlier FSP, adjust ISPEnable offset.\n"); } printk(FSP_INFO_LEVEL, "MIPI/ISP:\t\t%s\n", - UpdData->PcdEnableSdio?"Enabled":"Disabled"); + dev->enabled?"Enabled":"Disabled"); break; case EMMC_DEV_FUNC: /* EMMC 4.1*/ if ((dev->enabled) && -- cgit v1.2.3