From 2213843ae8971c2078997c5eba9e84ff3689a942 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Fri, 30 Jan 2015 20:56:05 -0700 Subject: fsp_baytrail: Get FSP reserved memory from the FSP HOB list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Because the pointer to the FSP HOB list is now being saved, we can use that to find the top of usable memory. This eliminates the need to hardcode the size of the FSP reserved memory area. Tested on minnowboard max for baytrail. The HOB structure used does not seem to be present for the rangeley or ivybridge/pantherpoint FSPs. At the very least, the GUID is not documented in the integration guides. Change-Id: I643e57655f55bfada60075b55aad2ce010ec4f67 Signed-off-by: Martin Roth Reviewed-on: http://review.coreboot.org/8308 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Aaron Durbin --- src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/soc/intel/fsp_baytrail/fsp') diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h index 1f4fa743b4..29309bf0a5 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h @@ -32,8 +32,6 @@ #include #include -#define FSP_RESERVE_MEMORY_SIZE 0x200000 - #define FSP_INFO_HEADER_GUID \ { \ 0x912740BE, 0x2284, 0x4734, {0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C} \ -- cgit v1.2.3