From 08bfba4f02f8d437357dba1a9523a9891ebd1351 Mon Sep 17 00:00:00 2001 From: Ben Gardner Date: Fri, 11 Mar 2016 16:29:54 -0600 Subject: intel/fsp_baytrail: Enable LPSS in ACPI mode This change fixes LPSS ACPI mode. Previously, enabling ACPI mode would result in unusable devices, as the resources were set to 0 and the devices were disabled. lpss.c was copied from intel/baytrail with a few minor adjustment for the different config structure. ACPI mode requires setting PcdLpssSioEnablePciMode==LPSS_PCI_MODE_DISABLE and applying the patch that disables clearing gnvs. https://review.coreboot.org/#/c/14040/ This doesn't handle the case where the FSP has PcdLpssSioEnablePciMode set to disable and the devicetree set to default. Change-Id: I12fffea3820ed948defe7a4f11af6b6363402560 Signed-off-by: Ben Gardner Reviewed-on: https://review.coreboot.org/14042 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/intel/fsp_baytrail/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/fsp_baytrail/Makefile.inc') diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index 65eb55f0b7..92b5f9804f 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -50,6 +50,7 @@ ramstage-y += reset.c ramstage-y += cpu.c ramstage-y += acpi.c ramstage-y += lpe.c +ramstage-y += lpss.c smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c -- cgit v1.2.3