From 1c3b1112fa2dbdd66b0470224715dc6da254ce62 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Fri, 19 Feb 2016 10:50:38 +0100 Subject: fsp_baytrail: Fix a possible hanging DisplayPort On some devices it can happen that DisplayPort TX lanes do not work properly if the power gate setup is omitted. If that happens, DisplayPort training will fail and therefore DisplayPort channel will not work. Both ports are affected. It seems that not every CPU shows this effect and those that are affected tend to fail more often in a cold environment. With this fix a board that originally shows this failure was running for over 1000 power cycles without issues. Change-Id: Ia266674490a1bee63a85b38d1dc949dcdf683cbc Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/13743 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: Paul Menzel --- src/soc/intel/fsp_baytrail/Kconfig | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/soc/intel/fsp_baytrail/Kconfig') diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 506e731f9f..b30d52f9df 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -96,6 +96,14 @@ config VGA_BIOS_FILE string default "../intel/cpu/baytrail/vbios/Vga.dat" if VGA_BIOS +config FSP_BAYTRAIL_GFX_INIT + default n + bool + help + Enabling this option will activate graphics init code. With this init, + the graphic power gate registers will be initialized before + VBIOS is executed. + config CPU_MICROCODE_HEADER_FILES string default "../intel/cpu/baytrail/microcode/M0130673322.h ../intel/cpu/baytrail/microcode/M0130679901.h ../intel/cpu/baytrail/microcode/M0230672228.h" -- cgit v1.2.3