From af27ac26b34216f4a188ee1738825177d469cf48 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 18 Feb 2022 00:44:15 +0530 Subject: soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code This patch moves `pmc_clear_pmcon_sts` function into common code and remove SoC specific instances. Accessing PMC GEN_PMCON_A register differs between different Intel chipsets. Typically, there are two possible ways to perform GEN_PMCON_A register programming (like `pmc_clear_pmcon_sts()`) as: 1. Using PCI configuration space when GEN_PMCON_A is a PCI configuration register. 2. Using MMIO access when GEN_PMCON_A is a memory mapped register. SoC users to select `SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION` Kconfig to perform GEN_PMCON_A register programming using PMC MMIO. BUG=b:211954778 TEST=Able to build brya. Signed-off-by: Subrata Banik Change-Id: I8d15f421c128630f928a1b6a7e2840056d68d7b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62064 Tested-by: build bot (Jenkins) Reviewed-by: Jeff Daly Reviewed-by: Tim Wawrzynczak Reviewed-by: Lean Sheng Tan --- src/soc/intel/elkhartlake/Kconfig | 1 + src/soc/intel/elkhartlake/include/soc/pm.h | 3 --- src/soc/intel/elkhartlake/pmutil.c | 14 -------------- 3 files changed, 1 insertion(+), 17 deletions(-) (limited to 'src/soc/intel/elkhartlake') diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index a1f7794c6c..b2d322cad9 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -58,6 +58,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET + select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/elkhartlake/include/soc/pm.h b/src/soc/intel/elkhartlake/include/soc/pm.h index 6ebbbfa170..6a86787068 100644 --- a/src/soc/intel/elkhartlake/include/soc/pm.h +++ b/src/soc/intel/elkhartlake/include/soc/pm.h @@ -155,9 +155,6 @@ uint16_t smbus_tco_regs(void); /* Set the DISB after DRAM init */ void pmc_set_disb(void); -/* Clear PMCON status bits */ -void pmc_clear_pmcon_sts(void); - /* STM Support */ uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ diff --git a/src/soc/intel/elkhartlake/pmutil.c b/src/soc/intel/elkhartlake/pmutil.c index 9bd431d025..0109215f2d 100644 --- a/src/soc/intel/elkhartlake/pmutil.c +++ b/src/soc/intel/elkhartlake/pmutil.c @@ -126,20 +126,6 @@ void pmc_set_disb(void) write8(addr, disb_val); } -void pmc_clear_pmcon_sts(void) -{ - uint32_t reg_val; - uint8_t *addr; - addr = pmc_mmio_regs(); - - reg_val = read32(addr + GEN_PMCON_A); - /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits - * while retaining MS4V write-1-to-clear bit */ - reg_val &= ~(MS4V); - - write32((addr + GEN_PMCON_A), reg_val); -} - /* * PMC controller gets hidden from PCI bus * during FSP-Silicon init call. Hence PWRMBASE -- cgit v1.2.3