From d2c57f2a0cdc3f07c2de278dfa4ae06bfb95f7bc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 17 Jan 2021 03:11:40 +0100 Subject: soc/intel/{skl,cnl,xsp,icl,tgl,ehl,adl,jsl}: use common LPC mirroring MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Drop the old, redundant code for mirroring LPC registers to DMI and make use of the new common code. Select the new Kconfig option for LPC DMI mirroring by the option SOC_INTEL_COMMON_PCH_BASE, which is selected by platforms starting with SPT, except APL and Xeon-SP. For Xeon-SP, select DMI and the new Kconfig directly. APL, even though it's younger than SPT, does not need mirroring. Test: Set LGMR address by calling `lpc_open_mmio_window` and check that both the PCI cfg and DMI LGMR register get written correctly. Tested successfully on clevo/cml-u. Change-Id: Ibd834f1474d986646bcebb754a17db97831a651f Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/49593 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/elkhartlake/espi.c | 24 ------------------------ 1 file changed, 24 deletions(-) (limited to 'src/soc/intel/elkhartlake/espi.c') diff --git a/src/soc/intel/elkhartlake/espi.c b/src/soc/intel/elkhartlake/espi.c index f33eca52c6..1737a474ac 100644 --- a/src/soc/intel/elkhartlake/espi.c +++ b/src/soc/intel/elkhartlake/espi.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -27,29 +26,7 @@ void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) gen_io_dec[3] = config->gen4_dec; } -void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) -{ - /* Mirror these same settings in DMI PCR */ - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]); -} - #if ENV_RAMSTAGE -static void soc_mirror_dmi_pcr_io_dec(void) -{ - struct device *dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 0); - uint32_t io_dec_arr[] = { - pci_read_config32(dev, ESPI_GEN1_DEC), - pci_read_config32(dev, ESPI_GEN2_DEC), - pci_read_config32(dev, ESPI_GEN3_DEC), - pci_read_config32(dev, ESPI_GEN4_DEC), - }; - /* Mirror these same settings in DMI PCR */ - soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); -} - void lpc_soc_init(struct device *dev) { /* Legacy initialization */ @@ -70,7 +47,6 @@ void lpc_soc_init(struct device *dev) pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); - soc_mirror_dmi_pcr_io_dec(); } #endif -- cgit v1.2.3