From 58ec51cc0aa3795d48b6d692a688017855d11baa Mon Sep 17 00:00:00 2001 From: Lean Sheng Tan Date: Wed, 9 Jun 2021 06:51:22 -0700 Subject: soc/intel/elkhartlake: Enable PCH GBE Enable PCH GBE with following changes: 1. Configure PCH GBE related FSP UPD flags 2. Use EHL own GBE ACPI instead of common code version due to different B:D.F from the usual GBE 3. Add kconfig PMC_EPOC to use the PMC XTAL read function Due to EHL GBE comes with time sensitive networking (TSN) capability integrated, EHL FSP is using 'PchTsn' instead of the usual 'PchLan' naming convention across the board. Signed-off-by: Lean Sheng Tan Change-Id: I6b0108e892064e804693a34e360034ae7dbee68f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55355 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/elkhartlake/acpi/southbridge.asl | 4 ++-- src/soc/intel/elkhartlake/acpi/tsn_glan.asl | 15 +++++++++++++++ 2 files changed, 17 insertions(+), 2 deletions(-) create mode 100644 src/soc/intel/elkhartlake/acpi/tsn_glan.asl (limited to 'src/soc/intel/elkhartlake/acpi') diff --git a/src/soc/intel/elkhartlake/acpi/southbridge.asl b/src/soc/intel/elkhartlake/acpi/southbridge.asl index ccad7760a3..059f220c0c 100644 --- a/src/soc/intel/elkhartlake/acpi/southbridge.asl +++ b/src/soc/intel/elkhartlake/acpi/southbridge.asl @@ -44,5 +44,5 @@ /* EMMC/SD card */ #include "scs.asl" -/* GbE 0:1f.6 */ -#include +/* GbE 0:1e.4 */ +#include "tsn_glan.asl" diff --git a/src/soc/intel/elkhartlake/acpi/tsn_glan.asl b/src/soc/intel/elkhartlake/acpi/tsn_glan.asl new file mode 100644 index 0000000000..de4f0b66a4 --- /dev/null +++ b/src/soc/intel/elkhartlake/acpi/tsn_glan.asl @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Intel PCH TSN Ethernet Controller 0:1e.4 */ + +Device(GTSN) { + Name(_ADR, 0x001E0004) + OperationRegion(TSRT,PCI_Config,0x00,0x100) + Field(TSRT,AnyAcc,NoLock,Preserve) + { + DVID, 16, + Offset(0x10), + TADL, 32, + TADH, 32, + } +} -- cgit v1.2.3