From 77653e3bceda70093a6a690097f99b71bafd7f03 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 12 Jul 2020 19:45:29 +0200 Subject: src: Drop useless GPE1 settings from FADT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit None of the currently-supported chips has a GPE1 block. The ACPI spec, version 6.3, section 4.8.1.6 (General-Purpose Event Registers) says: If a generic register block is not supported then its respective block pointer and block length values in the FADT table contain zeros. Since the FADT struct defaults to zero in coreboot, we don't need to do anything with GPE1 for now. So, drop the unneeded writes to GPE1 fields. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Iefc4bbc6e16fac12e0a9324d5a50b20aad59a6cd Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43379 Reviewed-by: Patrick Rudolph Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/soc/intel/denverton_ns/acpi.c | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'src/soc/intel/denverton_ns') diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 92a9c2a771..7d2d759032 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -121,14 +121,11 @@ void soc_fill_fadt(acpi_fadt_t *fadt) /* Power Control */ fadt->pm2_cnt_blk = pmbase + PM2_CNT; fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->gpe1_blk = 0; /* Control Registers - Length */ fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 8; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; @@ -210,13 +207,6 @@ void soc_fill_fadt(acpi_fadt_t *fadt) fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; fadt->x_gpe0_blk.addrh = 0x00; - - fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.access_size = 0; - fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; - fadt->x_gpe1_blk.addrh = 0x00; } static acpi_tstate_t denverton_tss_table[] = { -- cgit v1.2.3